Semiconductor package and manufacturing method thereof
A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer...
Gespeichert in:
Hauptverfasser: | , , , , |
---|---|
Format: | Patent |
Sprache: | chi ; eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | HSUEH, CHANG-JUNG WANG, KUAN-MIN CHANG, KUOIN CHUANG, JUIANG LIN, WEI-HUNG |
description | A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer includes a metallic thermal interface material (TIM) layer and a polymeric TIM layer adjacent to the metallic TIM layer. The polymeric TIM layer is located on corners of the semiconductor die from a top view. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW202310269A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW202310269A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW202310269A3</originalsourceid><addsrcrecordid>eNrjZDALTs3NTM7PSylNLskvUihITM5OTE9VSMxLUchNzCtNS0wuKS3KzEtXyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBjUvNSS-JDwo0MjIwNDYzMLB2NiVEDANbBLiM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor package and manufacturing method thereof</title><source>esp@cenet</source><creator>HSUEH, CHANG-JUNG ; WANG, KUAN-MIN ; CHANG, KUOIN ; CHUANG, JUIANG ; LIN, WEI-HUNG</creator><creatorcontrib>HSUEH, CHANG-JUNG ; WANG, KUAN-MIN ; CHANG, KUOIN ; CHUANG, JUIANG ; LIN, WEI-HUNG</creatorcontrib><description>A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer includes a metallic thermal interface material (TIM) layer and a polymeric TIM layer adjacent to the metallic TIM layer. The polymeric TIM layer is located on corners of the semiconductor die from a top view.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2023</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230301&DB=EPODOC&CC=TW&NR=202310269A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20230301&DB=EPODOC&CC=TW&NR=202310269A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HSUEH, CHANG-JUNG</creatorcontrib><creatorcontrib>WANG, KUAN-MIN</creatorcontrib><creatorcontrib>CHANG, KUOIN</creatorcontrib><creatorcontrib>CHUANG, JUIANG</creatorcontrib><creatorcontrib>LIN, WEI-HUNG</creatorcontrib><title>Semiconductor package and manufacturing method thereof</title><description>A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer includes a metallic thermal interface material (TIM) layer and a polymeric TIM layer adjacent to the metallic TIM layer. The polymeric TIM layer is located on corners of the semiconductor die from a top view.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2023</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDALTs3NTM7PSylNLskvUihITM5OTE9VSMxLUchNzCtNS0wuKS3KzEtXyE0tychPUSjJSC1KzU_jYWBNS8wpTuWF0twMim6uIc4euqkF-fGpxUBjUvNSS-JDwo0MjIwNDYzMLB2NiVEDANbBLiM</recordid><startdate>20230301</startdate><enddate>20230301</enddate><creator>HSUEH, CHANG-JUNG</creator><creator>WANG, KUAN-MIN</creator><creator>CHANG, KUOIN</creator><creator>CHUANG, JUIANG</creator><creator>LIN, WEI-HUNG</creator><scope>EVB</scope></search><sort><creationdate>20230301</creationdate><title>Semiconductor package and manufacturing method thereof</title><author>HSUEH, CHANG-JUNG ; WANG, KUAN-MIN ; CHANG, KUOIN ; CHUANG, JUIANG ; LIN, WEI-HUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW202310269A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2023</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HSUEH, CHANG-JUNG</creatorcontrib><creatorcontrib>WANG, KUAN-MIN</creatorcontrib><creatorcontrib>CHANG, KUOIN</creatorcontrib><creatorcontrib>CHUANG, JUIANG</creatorcontrib><creatorcontrib>LIN, WEI-HUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HSUEH, CHANG-JUNG</au><au>WANG, KUAN-MIN</au><au>CHANG, KUOIN</au><au>CHUANG, JUIANG</au><au>LIN, WEI-HUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package and manufacturing method thereof</title><date>2023-03-01</date><risdate>2023</risdate><abstract>A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer includes a metallic thermal interface material (TIM) layer and a polymeric TIM layer adjacent to the metallic TIM layer. The polymeric TIM layer is located on corners of the semiconductor die from a top view.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | chi ; eng |
recordid | cdi_epo_espacenet_TW202310269A |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | Semiconductor package and manufacturing method thereof |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T23%3A36%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HSUEH,%20CHANG-JUNG&rft.date=2023-03-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3ETW202310269A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |