Semiconductor package and manufacturing method thereof

Semiconductor package and manufacturing method thereof

A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: HSUEH, CHANG-JUNG, WANG, KUAN-MIN, CHANG, KUOIN, CHUANG, JUIANG, LIN, WEI-HUNG
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A semiconductor package includes a substrate, a semiconductor die, a lid, and an adhesive layer. The semiconductor die is attached to the substrate. The lid is over the semiconductor die and the substrate. The adhesive layer is sandwiched between the lid and the semiconductor die. The adhesive layer includes a metallic thermal interface material (TIM) layer and a polymeric TIM layer adjacent to the metallic TIM layer. The polymeric TIM layer is located on corners of the semiconductor die from a top view.