Semiconductor memory device having a dummy gate electrode arranged between the first gate electrode and the second gate electrode

A semiconductor memory device according to this invention includes: a substrate; a plurality of gate electrodes; a semiconductor layer facing the gate electrodes; a charge accumulation layer arranged between the gate electrodes and the semiconductor layer; a conductive layer connected to one end of the semiconductor layer; and a control circuit electrically connected to the gate electrodes and the conductive layer. The plurality of gate electrodes include: a first gate electrode; a second gate electrode farther away from the conductive layer than the first gate electrode; and a dummy gate electrode arranged between the first gate electrode and the second gate electrode. The control circuit is configured to be able to perform an erasing action. The erasing action includes: a first erasing voltage supply action for the conductive layer; a first programming action for the dummy gate electrode, performed after the first erasing voltage supply action; and a second erasing voltage supply operation performed after t