Memory device which includes a memory array, control circuits, pre-charging circuits, a standby activation circuit, high voltage level control circuits, write word line control circuits, read word line control circuits, and a write driving circuit

The present invention proposes a memory device, which mainly includes a memory array (1), a plurality of control circuits (2), a plurality of pre-charging circuits (3), a standby activation circuit (4), a plurality of high voltage level control circuits (5), a plurality of write word line control circuits (6), a plurality of read word line control circuits (7), and a write driving circuit (8). As such, in a write mode, a combination of the plurality of control circuits (2), the plurality of write word line control circuits (6), and the plurality of write driving circuits (8) effectively increases a writing speed, while preventing difficulty of writing logic 1, and in a read mode, a combination of the plurality of control circuits (2), the plurality of high voltage level control circuits (5), and the plurality of read word line control circuits (7) prevents unnecessary consumption of power, while increasing a reading speed. Further, in a static random access memory (SRAM) cell according to the present inventio