Gate driving circuit

A gate driving circuit is provided. The gate driving circuit includes a plurality of shift register circuits coupled in series, where a Nth stage shift register circuit includes a pull-up circuit, a pull-down circuit, a voltage stabilizing circuit, an output stage circuit, and a first capacitor. The pull-up circuit pulls up a first driving signal. The pull-down circuit pulls down the first driving signal according to a first clock signal. The voltage stabilizing circuit stabilizes the voltage of the first driving signal according to a DC common voltage. The output stage circuit generates a Nth stage gate driving signal according to the first driving signal and the second driving signal. The first capacitor receives the first driving signal on the first electrode of the first capacitor. The first capacitor receives the Nth stage gate driving signal on the second electrode of the first capacitor.