Semiconductor memory device

A semiconductor memory device of an embodiment includes a substrate, a plurality of first conductor layers, a pillar, and a second conductor layer. The plurality of first conductor layers are provided above the substrate, and are separated from each other in a first direction. The pillar is provided penetrating the plurality of first conductor layers, and includes a first semiconductor layer stretched in the first direction. The intersecting portion of the pillar and the first conductor layer functions as a memory cell. The second conductor layer is provided above the plurality of first conductor layers, and is in contact with the first semiconductor layer. The second conductor layer is metal or silicide.