Multi-layer semiconductor package with stacked passive components

A semiconductor package (100) includes a first layer (104) including a semiconductor die (130) embedded within a dielectric substrate (128), and a first set of metal pillars (122) extending through the dielectric substrate, a second layer (106) stacked on the first layer, the second layer including a metal trace (150) patterned on the dielectric substrate of the first layer, a passive component (141) including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars (152) extending from the metal trace to an opposing side of the second layer, and a third layer (108) stacked on the second layer, the third layer including at least one inductor (170) electrically coupled to metal pillars of the second set of metal pillars.