Micro-ic massive testing

A micro-integrated circuit massive testing system includes: a first test area, including a plurality of test pads and a plurality of reading pads, disposed on scribe lines; a plurality of test controllers are disposed on the scribe lines one by one; a probes, configured to contact the first test area to test a plurality of rows of integrated circuit chip; each of test controllers is configured to test a respective one of the plurality of rows of integrated circuit chips row by row; wherein, the probe merely contact the first test area once; wherein, the plurality of read pads are configured to read the test results of each of the plurality of rows of integrated circuit chips row by row.