Graphene barrier for electrical interconnects and producing method thereof

Techniques are disclosed for producing graphitic barrier layers that encapsulate or otherwise isolate a metal interconnect feature from adjacent insulator or dielectric materials. The techniques can include an on-chip synthesis method in which barrier layer precursor materials, for example, hydrocar...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CAUDILLO, ROMAN, MAESTRE CARO, ARANZAZU
Format: Patent
Sprache:chi ; eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Techniques are disclosed for producing graphitic barrier layers that encapsulate or otherwise isolate a metal interconnect feature from adjacent insulator or dielectric materials. The techniques can include an on-chip synthesis method in which barrier layer precursor materials, for example, hydrocarbon-based self-assembled monolayers, are positioned between a dielectric feature and an electrically conductive metal line. Through a treatment process, such as thermal annealing, the barrier layer precursor materials are converted into a graphitic barrier layer that comprises graphene and, in some cases, is a graphene monolayer. The disclosed graphitic barrier layers may be atomically thin, have a substantially uniform thickness and may optionally conduct charge, thereby allowing the barrier layer to serve as a current shunt, capable of supporting high current densities.