Internal latch circuit and method for generating latch signal thereof

An internal latch circuit having a plurality of low initial value D flip-flops, a plurality of high initial value D flip-flops, an internal latch signal generating circuit and a NAND gate, and a method for generating latch signal thereof is provided. First, an input delay signal in response to a clock signal is generated. Then, a first internal input signal, a first reverse internal input signal, a second internal input signal, and a second reverse internal input signal are generated by using the low initial value D flip-flops and the high initial value D flip-flops, based on the internal data strobe signal and in response to the input delay signal, and are transmitted to the internal latch signal generating circuit. Then, the internal latch signal generating circuit outputs the first reverse pre-output signal and the second reverse pre-output signal. Finally, an internal latch signal is generated through a NAND gate.