Semiconductor memory device

Embodiments provide a semiconductor memory device capable of reducing a chip area. According to one embodiment, a semiconductor memory device includes a substrate (50), a first memory cell, a first bit line (BL), a first word line (WL), a first transistor (T8), and a second transistor (TR7). The first memory cell is provided above the substrate (50). The first bit line (BL) extends in the first direction and is connected to the first memory cell. The first word line (WL) extends in a second direction intersecting the first direction and is connected to the first memory cell. The first transistor (T8) is provided on the substrate (50) and is connected to the first bit line (BL). The second transistor (TR7) is provided below the first memory cell and on the substrate (50), and is connected to the first word line (WL).