Analog to digital converter device and method for calibrating clock skew

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit includes a first adjusting circuit. The first adjusting circuit is configured to analyze time difference information in even-numbered sampling periods of the clock signals according to the second quantized outputs and adjusting information, in order to generate adjustment signals. The adjustment signals are for reducing a clock skew in the ADC circuitries.