Clock gating cell

A clock gating cell is provided. The clock gating cell comprises two latches configured as a flip-flop to store the value of the input terminal by using the positive/negative edge of the first clock signal, and the clock gating cell further comprises a selector configured for selecting the different input terminals. Further, in the non-scan testing mode, the clock gating cell can forcibly turn off the unused latch through an independent signal to achieve power saving effect, and during the scan shift and the scan capture of the scan testing mode, the clock gating cell can forcibly outputs the first clock signal as a gating clock signal through another two independent signals respectively.