Digital circuit robustness verification method and system

A digital circuit robustness verification method is provided that includes the steps outlined below. An internal storage circuit and an external storage circuit corresponding to an under-test circuit are set to store a plurality of random values and a configuration of the under-test circuit for performing a predetermined function is set by a processing circuit. A driving signal corresponding to the predetermined function is transmitted to the under-test circuit by a former stage circuit such that the under-test circuit executes the predetermined function to further generate an output signal. Whether the output signal is correct is determined by a latter stage circuit to determine the under-test circuit passes a robustness verification when the output signal is correct.