Memory gate driver technology for flash memory cells
A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the fi...
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| Sprache: | chi ; eng |
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| Zusammenfassung: | A memory array including a first memory cell including a first memory gate coupled to receive a first signal. The memory array including a second memory cell including a first memory gate coupled to receive a second signal. The magnitude of the second signal is different than the magnitude of the first signal. The memory array including a third memory cell including a first memory gate coupled to receive a third signal. The magnitude of the third signal is different than the magnitude of the first signal and the magnitude of the second signal. The first signal, the second signal and the third signal are received concurrently. |
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