Memory storage apparatus and method for testing memory storage apparatus
A memory storage apparatus including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory cells. The memory cell array stores data. The memory control circuit is coupled to the memory cell array. The memory control circuit applies one of...
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| Format: | Patent |
| Sprache: | chi ; eng |
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| Zusammenfassung: | A memory storage apparatus including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory cells. The memory cell array stores data. The memory control circuit is coupled to the memory cell array. The memory control circuit applies one of a set signal and a reset signal to a target memory cell of the memory cells to generate a read current. The memory control circuit compares the read current to a reference current. The memory control circuit determines whether the target memory cell is failed according to a comparison result. In addition, a method for testing a memory storage apparatus is also provided. |
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