Memory bank apparatus, static random access memory apparatus and random access memory apparatus

The invention provides a memory bank apparatus, a static random access memory apparatus and a random access memory. According to one general aspect, an apparatus may include a global bit line, and a plurality of memory banks. The global bit line may be configured to facilitate a memory access. Each memory bank may include a local keeper-precharge circuit coupled between a power supply and the global bit line, and a control circuit configured to control, at least in part, the local keeper-precharge circuit. The control circuit is configured to prevent or reduce contention between the local keeper/precharge circuit and other portions of the memory bank or other memory banks.