Bit-flipping LDPC decoding algorithm with hard channel information

Bit-flipping LDPC decoding algorithm with hard channel information

Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of t...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: XIONG, CHEN-RONG, BHATIA, AMAN, CHOU, HARRIS HONG-ZHI, PRABHAKAR, ABHIRAM, KUMAR, NAVEEN, ZHANG, FAN
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
CALCULATING
CODE CONVERSION IN GENERAL
CODING
COMPUTING
COUNTING
DECODING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRICITY
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:Memory systems may include a memory storage, and an error correcting code (ECC) unit suitable for determining a number of unsatisfied check nodes of a channel output in a decoding iteration of a decoding process, updating a flipping indicator of a variable node, comparing the flipping indicator of the variable node with a flipping threshold associated with the decoding process, flipping a bit of the variable node when the flipping indicator is greater than the flipping threshold, and ending the decoding process when decoding is determined to be successful or a maximal iteration number is reached.