Dual port static random access memory with standby initiation circuit to enter the standby mode quickly, and a high voltage level control circuits for increasing the reading speed

The present invention proposes a dual port static random access memory (SRAM), which mainly comprises a memory array (1), plural control circuits (2), plural precharge circuits (3), a standby initiation circuit (4), and plural high voltage level control circuits (5). The memory array is formed of plural rows of memory cells and plural columns of memory cells. Each row of memory cells is provided with a control circuit. Each memory cell (1) comprises a first inverter (formed of a first PMOS transistor P11 and a first NMOS transistor M11), a second inverter (formed of a second PMOS transistor P12 and a second NMOS transistor M12), an access transistor (formed of the third NMOS transistor M13), a first reading transistor (M14) and a second reading transistor (M15). Each control unit (2) is connected to the source of the first NMOS transistor (M11) and the source of the second NMOS transistor (M12) in each memory cell of the memory cells in the corresponding row, so as to control the source voltage of the first N