Multi-processor system and cache sharing method

Multi-processor system and cache sharing method

Multi-processor system and cache sharing method is provided. The multi-processor system comprises a plurality of processor sub-systems and a cache coherence interconnect circuit. The processor sub-systems have a first processor sub-system and a second processor sub-system. The first processor sub-sy...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: CHIAO, WEI-HAO, CHANG, MING-KU, HSU, CHIA-HAO, LIN, CHIEN-HUNG, CHANG, SHUNIEH, HSIAO, PING, WU, MING-JU, LEE, KUN-GENG
Format: Patent
Sprache:chi ; eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Multi-processor system and cache sharing method is provided. The multi-processor system comprises a plurality of processor sub-systems and a cache coherence interconnect circuit. The processor sub-systems have a first processor sub-system and a second processor sub-system. The first processor sub-system includes at least one first processor and a first cache coupled to the at least one first processor. The second processor sub-system includes at least one second processor and a second cache coupled to the at least one second processor. The cache coherence interconnect circuit is coupled to the processor sub-systems, and used to obtain a cache line data from an evicted cache line in the first cache, and transfer the obtained cache line data to the second cache for storage.