Memory system and memory physical layer interface circuit

A memory physical layer interface circuit electrically connected between a memory controller and a memory device is provided. The memory physical layer interface circuit includes a clock generation module and first-in-first-out (FIFO) modules. The clock generation module generates a reference clock signal and output related clock signals. The reference clock signal is transmitted to the memory device. Each of the FIFO modules writes the input information transmitted by the memory controller therein according to a write-related clock signal and retrieves the input information according to one of the output related clock signals to generate an output signal. The output signal is transmitted to the output signal to operate the memory device. The write-related clock signal is generated by dividing a frequency of one of the output related clock signals.