Epitaxial wafer for semiconductor transistor and semiconductor transistor

To provide an epitaxial wafer for a semiconductor transistor capable of making the electrical resistance of a specific semiconductor layer lower than conventional, and making the current gain of a semiconductor transistor larger than conventional, and to provide a semiconductor transistor using the...

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Bibliographische Detailangaben
Hauptverfasser: MEGURO, TAKESHI, FUJIO, SHINJIRO
Format: Patent
Sprache:chi ; eng
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Beschreibung
Zusammenfassung:To provide an epitaxial wafer for a semiconductor transistor capable of making the electrical resistance of a specific semiconductor layer lower than conventional, and making the current gain of a semiconductor transistor larger than conventional, and to provide a semiconductor transistor using the same. An epitaxial wafer for a semiconductor transistor includes a semiconductor layer added with n-type impurities, i.e., Te, at a concentration of 9.0 x 1018cm-39.0 x 1019cm-3. Preferably, the semiconductor layer is a sub-collector layer.