Implementation of variable length instruction encoding using alias addressing

A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operation mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.