Chip stacking structure

A chip stacking structure including a plurality of microbump structures, at least one first space layer, a plurality of first substrates, a plurality of second substrates and at least one second space layer is provided. The first substrates are stacked on one another by using a part of the microbump structures, and each of the first substrates includes at least one first redistribution layer. The first space layer is located between the stacked first substrates. The second substrates are stacked on at least one of the first substrates by using another part of the microbump structures, and each of the second substrates includes at least one second redistribution layer. The second space layer is located between the stacked first and second substrates. The first redistribution layer, the second redistribution layer and the microbump structures form a plurality of impedance components, and the impedance components provide a specific oscillation frequency.