Semiconductor package structure and manufacturing method thereof
Semiconductor package structure including a carrier, a chip, a plurality of bonding wires and a molding compound is provided. The carrier has a die pad and a plurality of leads disposed around the die pad. The chip is disposed on the die pad of the carrier. The bonding wires are disposed between the...
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| creator | TSAI, YU-FANG CHIANG, PO-SHING HU, PINGNG |
| description | Semiconductor package structure including a carrier, a chip, a plurality of bonding wires and a molding compound is provided. The carrier has a die pad and a plurality of leads disposed around the die pad. The chip is disposed on the die pad of the carrier. The bonding wires are disposed between the chip and the leads. The molding compound encapsulates the chip, the bonding wires and a portion of the leads. The molding compound has an upper surface and a lower surface opposite to each other and a side surface connecting the upper surface and the lower surface. An included angle between the side surface and the surface normal of the lower surface is more than 0 degree. |
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| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_TW201248805A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>TW201248805A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_TW201248805A3</originalsourceid><addsrcrecordid>eNrjZHAITs3NTM7PSylNLskvUihITM5OTE9VKC4pAgqUFqUqJOalKOQm5pWmJYL4mXnpCrmpJRn5KQolGalFqflpPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tRhoYGpeakl8SLiRgaGRiYWFgamjMTFqADSdMkg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Semiconductor package structure and manufacturing method thereof</title><source>esp@cenet</source><creator>TSAI, YU-FANG ; CHIANG, PO-SHING ; HU, PINGNG</creator><creatorcontrib>TSAI, YU-FANG ; CHIANG, PO-SHING ; HU, PINGNG</creatorcontrib><description>Semiconductor package structure including a carrier, a chip, a plurality of bonding wires and a molding compound is provided. The carrier has a die pad and a plurality of leads disposed around the die pad. The chip is disposed on the die pad of the carrier. The bonding wires are disposed between the chip and the leads. The molding compound encapsulates the chip, the bonding wires and a portion of the leads. The molding compound has an upper surface and a lower surface opposite to each other and a side surface connecting the upper surface and the lower surface. An included angle between the side surface and the surface normal of the lower surface is more than 0 degree.</description><language>chi ; eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121201&DB=EPODOC&CC=TW&NR=201248805A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20121201&DB=EPODOC&CC=TW&NR=201248805A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TSAI, YU-FANG</creatorcontrib><creatorcontrib>CHIANG, PO-SHING</creatorcontrib><creatorcontrib>HU, PINGNG</creatorcontrib><title>Semiconductor package structure and manufacturing method thereof</title><description>Semiconductor package structure including a carrier, a chip, a plurality of bonding wires and a molding compound is provided. The carrier has a die pad and a plurality of leads disposed around the die pad. The chip is disposed on the die pad of the carrier. The bonding wires are disposed between the chip and the leads. The molding compound encapsulates the chip, the bonding wires and a portion of the leads. The molding compound has an upper surface and a lower surface opposite to each other and a side surface connecting the upper surface and the lower surface. An included angle between the side surface and the surface normal of the lower surface is more than 0 degree.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZHAITs3NTM7PSylNLskvUihITM5OTE9VKC4pAgqUFqUqJOalKOQm5pWmJYL4mXnpCrmpJRn5KQolGalFqflpPAysaYk5xam8UJqbQdHNNcTZQze1ID8-tRhoYGpeakl8SLiRgaGRiYWFgamjMTFqADSdMkg</recordid><startdate>20121201</startdate><enddate>20121201</enddate><creator>TSAI, YU-FANG</creator><creator>CHIANG, PO-SHING</creator><creator>HU, PINGNG</creator><scope>EVB</scope></search><sort><creationdate>20121201</creationdate><title>Semiconductor package structure and manufacturing method thereof</title><author>TSAI, YU-FANG ; CHIANG, PO-SHING ; HU, PINGNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_TW201248805A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>chi ; eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>TSAI, YU-FANG</creatorcontrib><creatorcontrib>CHIANG, PO-SHING</creatorcontrib><creatorcontrib>HU, PINGNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TSAI, YU-FANG</au><au>CHIANG, PO-SHING</au><au>HU, PINGNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Semiconductor package structure and manufacturing method thereof</title><date>2012-12-01</date><risdate>2012</risdate><abstract>Semiconductor package structure including a carrier, a chip, a plurality of bonding wires and a molding compound is provided. The carrier has a die pad and a plurality of leads disposed around the die pad. The chip is disposed on the die pad of the carrier. The bonding wires are disposed between the chip and the leads. The molding compound encapsulates the chip, the bonding wires and a portion of the leads. The molding compound has an upper surface and a lower surface opposite to each other and a side surface connecting the upper surface and the lower surface. An included angle between the side surface and the surface normal of the lower surface is more than 0 degree.</abstract><oa>free_for_read</oa></addata></record> |
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| language | chi ; eng |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Semiconductor package structure and manufacturing method thereof |
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