Method for exposing through-base wafer vias for fabrication of stacked devices

Method for exposing through-base wafer vias for fabrication of stacked devices

An effective method for forming through-base wafer vias for the fabrication of stacked devices, such as electronic devices, is described. The base wafer can be a silicon wafer, in which case the method relates to TSV (through-silicon via) technology. The method affords high removal rates of silicon...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: CASTILLO, DANIEL HERNANDEZ II, KIM, HYOUNG-SIK, HENRY, JAMES MATTHEW, LEE, JUNG-HEE
Format: Patent
Sprache:chi ; eng
Schlagworte:
ADHESIVES
BASIC ELECTRIC ELEMENTS
CHEMISTRY
DYES
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FORELSEWHERE
METALLURGY
MISCELLANEOUS APPLICATIONS OF MATERIALS
MISCELLANEOUS COMPOSITIONS
NATURAL RESINS
PAINTS
POLISHES
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:An effective method for forming through-base wafer vias for the fabrication of stacked devices, such as electronic devices, is described. The base wafer can be a silicon wafer, in which case the method relates to TSV (through-silicon via) technology. The method affords high removal rates of silicon under appropriate conditions.