Loopback test architecture and method

A loopback test architecture is provided. The loopback test architecture includes a voltage adjuster, a DAC and an ADC. The voltage adjuster includes a gain control module including a voltage scale-up circuit and a voltage scale-down circuit and an offset control module. During a DAC test mode, the DAC generates a series of first analog test signals to be scaled up by the voltage scale-up circuit. The ADC converts the first analog test signals into a plurality of voltage values. During an ADC test mode, the DAC generates a series of analog test signal groups to be scaled down and offset by the voltage scale-up circuit and the offset control module. The ADC further converts the analog test signal group into a plurality of code hits, wherein each analog test signal group corresponds to a scale-range of the ADC. A loopback test method is disclosed herein as well.