Method for forming through-base wafer vias for fabrication of stacked devices

An effective chemical mechanical planarization (CMP) method is provided for forming vias in silicon wafers for the fabrication of stacked devices using TSV(through-silicon via) technology. The method affords high removal rates of both metal (e.g., copper) and silicon such that a need for a grinding...

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Bibliographische Detailangaben
Hauptverfasser:	CASTILLO, DANIEL HERNANDEZ II, HENRY, JAMES MATTHEW
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	ADHESIVES BASIC ELECTRIC ELEMENTS CHEMISTRY DYES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FORELSEWHERE METALLURGY MISCELLANEOUS APPLICATIONS OF MATERIALS MISCELLANEOUS COMPOSITIONS NATURAL RESINS PAINTS POLISHES POLISHING COMPOSITIONS OTHER THAN FRENCH POLISH SEMICONDUCTOR DEVICES SKI WAXES
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Beschreibung
Zusammenfassung:	An effective chemical mechanical planarization (CMP) method is provided for forming vias in silicon wafers for the fabrication of stacked devices using TSV(through-silicon via) technology. The method affords high removal rates of both metal (e.g., copper) and silicon such that a need for a grinding step prior to CMP processing may not be necessary. The method affords an approximately 1: 1 Cu: Si selectivity for removal of silicon and copper under appropriate conditions and the Cu: Si selectivity is tunable.by adjustment of levels of some key components.