Method, apparatus and system of parallel IC test

Method, apparatus and system of parallel IC test

What is disclosed is a method, apparatus and system for parallel testing a plurality of integrated circuit devices under test (DUTs) on a common substrate, that identical input stimulations are applied to each of the plurality of DUTs, that the output terminal of each of the plurality of DUTs are co...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: ZHANG, BINGUN, LIN, KENNETH C, REN, HAO-QI, GENG, HONG-XI, ZHENG, CHANGUN
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
SEMICONDUCTOR DEVICES
TESTING
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Beschreibung
Zusammenfassung:What is disclosed is a method, apparatus and system for parallel testing a plurality of integrated circuit devices under test (DUTs) on a common substrate, that identical input stimulations are applied to each of the plurality of DUTs, that the output terminal of each of the plurality of DUTs are compared against the corresponding output terminal of other DUTs or against a expected output result, and base on the results of the said comparisons to separate the mal-functioned DUTs from the normal function DUTs. This invention lowers testing cost, reduces production time and lowers the test error rate.