Substrate and chip packaging structure

The invention discloses a substrate for carrying a chip. The substrate of the invention comprises a first surface and a wiring layer, wherein the wiring layer is disposed on the first surface, and at least one non-wiring area was formed on the wire layer. When the chip is carried on the substrate, the first surface of the substrate faces the active surface of the chip and the wiring layer of the substrate is electrically connected to the chip, and simultaneously, a projection area formed by a fuse arrangement area on the active surface of the chip vertically projecting on the first surface of the substrate is located within the scope of the non-wiring area of the wiring layer of the substrate.