Method for post-routing redundant via insertion in integrated circuit layout

The present invention provides a method for post-routing redundant via insertion in IC layout. The method is to construct a conflict graph from a post-routing design first, then find a maximal independent set (MIS) of the conflict graph, and finally replace a single via with a double via for each ve...

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Bibliographische Detailangaben
Hauptverfasser:	WANG, TINGI, LEE, KUANG-YAO
Format:	Patent
Sprache:	chi ; eng
Schlagworte:	CALCULATING COMPUTING CONTROL OR REGULATING SYSTEMS IN GENERAL CONTROLLING COUNTING ELECTRIC DIGITAL DATA PROCESSING FUNCTIONAL ELEMENTS OF SUCH SYSTEMS MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS ORELEMENTS PHYSICS REGULATING
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Beschreibung
Zusammenfassung:	The present invention provides a method for post-routing redundant via insertion in IC layout. The method is to construct a conflict graph from a post-routing design first, then find a maximal independent set (MIS) of the conflict graph, and finally replace a single via with a double via for each vertex in the maximal independent set. Besides, since redundant vias can be classified into on-track and off-track ones, and on-track ones have better electrical properties, the invention also present two methods to increase the amount of on-track redundant vias while a redundant via insertion solution is given.