Cavity chip package

Cavity chip package

A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates a support which securely holds the...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: TANARY, SUSANTO, SUN, YI-SHENG ANTHONY, IKSAN, HENRY, TAN, HIEN-BOON, KIM, SEONG-KWANG BRANDON
Format: Patent
Sprache:chi ; eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A package for an IC includes a carrier with a cavity formed on one of the major surfaces. Bumps of a semiconductor die are mated to contact pads located on the bottom of the cavity. The die is attached to the major surface of the carrier. The major surface creates a support which securely holds the chip in place with adhesive for assembly.