A shuttle mask layout method and a semiconductor element producing method using the same

A new shuttle mask layout method and a semiconductor element producing method using the same are provided. Several customers' circuit designs are commonly layout in a mass-production like shuttle mask. A major circuit design, needing many samples much more than those a conventional shuttle provides and possibly directing to mass production, takes more seats in center/major areas of the mask. Other circuit designs, only subject to silicon verification and not directing to mass production as this timeframe, take fewer seats in boundary area on one end of the mask. Then, engineering samples are produced based on the mass-product like shuttle mask. If the verification result of the major circuit design is passed, the boundary area of the mask, corresponding to non-major circuit designs, are blinded out and a mass-production mask with only the major circuit design is made. Then the major circuit design can go mass-production directly with the mass-production mask without re-generating a new full set of masks.