Clock generating device

A clock generating device is disclosed for being capable of discarding a buffer memory that is necessary heretofore within a data transmitting interface while utilizing a spectral dispersion clock upon an action of each circuit portion within a system, easily adopting the spectral dispersion clock as an action clock within the system, and achieving a high performance of the system, wherein the phase of the reference clock occurred by the oscillator 1 is controlled by the variable delay circuit 2. The variable delay circuit 2 is capable of changing the configuration of the control voltage in every clock cycle and working on the phase modulation of the reference clock by the delay configuration circuit 11. The spectral dispersion is occurred by the configuration having the cycle of the output modulation clock changed. Further, the delay configuration circuit 11 guaranties a certain synchronization within the dispersion clock by detecting the output condition (the clock edge) of the delay element of the variable