Device for stabilization of high-performance pulsed discharge of pulsed plasma generator to magnetron sputtering

Device for stabilization of the high-power pulsed discharge of the pulsed plasma generator to the magnetron sputtering is characterised by inserting a power protection resistor (R17) with a low value of parasitic inductance wound with an Ayrton-Perry type winding wire or power protective resistor (R...

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Hauptverfasser: Meško, Marcel, Bohovičová, Jana, Čaplovič, Ľubomír, Sýkora, Roman
Format: Patent
Sprache:eng ; slo
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Zusammenfassung:Device for stabilization of the high-power pulsed discharge of the pulsed plasma generator to the magnetron sputtering is characterised by inserting a power protection resistor (R17) with a low value of parasitic inductance wound with an Ayrton-Perry type winding wire or power protective resistor (R17) with a low value of parasitic inductance based on thin films into the power supply branch of the magnetron (6) with NMOS transistor (5). The value of the impedance of the power protective resistor (R17) is equal to the impedance of the melting discharge in metal vapors. Electronic control circuits are connected to the gate of the IGBT transistor (5) of the NMOS. Between the source electrode and the drain electrode of the NMOS transistor (5) is connected in parallel the first branch of the ninth resistor (R9), the tenth resistor (R10), the fourth capacitor (C4), the second branch with the third diode (D3) and the third branch with two overvoltage diodes (TRANSIL1, TRANSIL2), and compensation capacitors (CE1 to CE6) and compensation resistors (R15 and R16) are connected between the positive and negative terminals of the power supply between the positive and negative terminals of the power supply. A protective diode (D5), a fourth diode (D4), stabilizing resistors (R12 and R13) and an eleventh resistor (R11) connected to the negative terminal of the power supply are included in the power supply branch of the magnetron (6). The electronic control circuits of the gate of the IGBT transistor (5) NMOS are formed by a frequency generator with a switch and supporting elements and are further formed by an IGBT driver (4) with supporting elements, among which a switch (3) with a second ARDUINO input is included. Zapojenie stabilizácie vysokovýkonného impulzného výboja pulzného plazmového generátora na magnetrónové naprašovanie je riešené tak, že do výkonovej napájacej vetvy magnetrónu (6) s tranzistorom (5) NMOS je zaradený výkonový ochranný odpor (R17) s nízkou hodnotou parazitnej indukčnosti vinutý drôtom s vinutím typu Ayrton-Perry alebo výkonový ochranný odpor (R17) s nízkou hodnotou parazitnej indukčnosti na báze tenkých vrstiev, kde hodnota impedancie výkonového ochranného odporu (R17) sa rovná impedancii tlecieho výboja v parách kovov. Na hradlo IGBT tranzistora (5) NMOS sú pripojené elektronické riadiace obvody. Medzi source elektródu a drain elektródu tranzistora (5) NMOS je paralelne zaradená prvá vetva deviateho odporu (R9), desiateho odporu (R10), štvrtého