Lead-on-chip semiconductor device

A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have on-chip portions (36, 38) which are electrically coupled to peripheral bond pads (14) by conductive wires (30) and off-chip portions (42). On-chip portions (38) of the leads extend from the central portions toward centerline A-A for improved adhesion. At least one on-chip portion (28) is forked and includes a branch which lacks a direct wire bond connect, also for improved adhesion. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.