PROCESS FOR FABRICATING A HETEROSTRUCTURE WITH MINIMIZED STRESS

PROCESS FOR FABRICATING A HETEROSTRUCTURE WITH MINIMIZED STRESS

PROCESS FOR FABRICATING A HETEROSTRUCTURE WITH MINIMIZED STRESSProcess for fabricating a heterostructure comprising a step (S5) of bonding a first wafer (110) to a second wafer (120), the first wafer (110) having a thermal expansion coefficient that is lower than the thermal expansion coefficient of...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: VAUFREDAZ, ALEXANDRE
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROCESS FOR FABRICATING A HETEROSTRUCTURE WITH MINIMIZED STRESSProcess for fabricating a heterostructure comprising a step (S5) of bonding a first wafer (110) to a second wafer (120), the first wafer (110) having a thermal expansion coefficient that is lower than the thermal expansion coefficient of the second wafer (120), and at least one bond-strengthening annealing step (S7). The process is particularly characterized in that it comprises, after the bonding step (S5) and before the bond-strengthening annealing step (S7), at least one trimming step (S5) in which the first wafer (110) is at least partially trimmed.(Figures 4C & 4D)