DUAL REDUNDANT FAULT TOLERANT ELECTRONIC SYSTEM AND METHOD
Embodiments of the present invention provide a fault tolerant system for electronic components, the system comprising: a first Versa Module Eurocard (VME) module located within a housing; and a second Versa Module Eurocard (VME) module located within the housing; wherein the first and second VME mod...
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creator | CHYE GERALD LEE THIAN HUNTER RICHARD STEPHEN FAI WONG CHUNG |
description | Embodiments of the present invention provide a fault tolerant system for electronic components, the system comprising: a first Versa Module Eurocard (VME) module located within a housing; and a second Versa Module Eurocard (VME) module located within the housing; wherein the first and second VME modules are functionality. Each of the first and second modules may be located on a single backplane. Each of the first and second modules may further include: a plurality of card slots; a CPU card in one of the plurality of card slots; an input/output (I/O) card in one of the card slots and at least one input/output (I/O) channel providing an external connection to the system, the I/O channel being electrically connected to a plurality of user defined I/O connections on each of the VME modules. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_SG159415A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>SG159415A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_SG159415A13</originalsourceid><addsrcrecordid>eNrjZLByCXX0UQhydQn1c3H0C1Fwcwz1CVEI8fdxDQJxXX1cnUOC_P08nRWCI4NDXH0VHP1cFHxdQzz8XXgYWNMSc4pTeaE0N4O8m2uIs4duakF-fGpxQWJyal5qSXywu6GppYmhqaOhMWEVACD8KFQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>DUAL REDUNDANT FAULT TOLERANT ELECTRONIC SYSTEM AND METHOD</title><source>esp@cenet</source><creator>CHYE GERALD LEE THIAN ; HUNTER RICHARD STEPHEN ; FAI WONG CHUNG</creator><creatorcontrib>CHYE GERALD LEE THIAN ; HUNTER RICHARD STEPHEN ; FAI WONG CHUNG</creatorcontrib><description>Embodiments of the present invention provide a fault tolerant system for electronic components, the system comprising: a first Versa Module Eurocard (VME) module located within a housing; and a second Versa Module Eurocard (VME) module located within the housing; wherein the first and second VME modules are functionality. Each of the first and second modules may be located on a single backplane. Each of the first and second modules may further include: a plurality of card slots; a CPU card in one of the plurality of card slots; an input/output (I/O) card in one of the card slots and at least one input/output (I/O) channel providing an external connection to the system, the I/O channel being electrically connected to a plurality of user defined I/O connections on each of the VME modules.</description><language>eng</language><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100330&DB=EPODOC&CC=SG&NR=159415A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100330&DB=EPODOC&CC=SG&NR=159415A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHYE GERALD LEE THIAN</creatorcontrib><creatorcontrib>HUNTER RICHARD STEPHEN</creatorcontrib><creatorcontrib>FAI WONG CHUNG</creatorcontrib><title>DUAL REDUNDANT FAULT TOLERANT ELECTRONIC SYSTEM AND METHOD</title><description>Embodiments of the present invention provide a fault tolerant system for electronic components, the system comprising: a first Versa Module Eurocard (VME) module located within a housing; and a second Versa Module Eurocard (VME) module located within the housing; wherein the first and second VME modules are functionality. Each of the first and second modules may be located on a single backplane. Each of the first and second modules may further include: a plurality of card slots; a CPU card in one of the plurality of card slots; an input/output (I/O) card in one of the card slots and at least one input/output (I/O) channel providing an external connection to the system, the I/O channel being electrically connected to a plurality of user defined I/O connections on each of the VME modules.</description><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLByCXX0UQhydQn1c3H0C1Fwcwz1CVEI8fdxDQJxXX1cnUOC_P08nRWCI4NDXH0VHP1cFHxdQzz8XXgYWNMSc4pTeaE0N4O8m2uIs4duakF-fGpxQWJyal5qSXywu6GppYmhqaOhMWEVACD8KFQ</recordid><startdate>20100330</startdate><enddate>20100330</enddate><creator>CHYE GERALD LEE THIAN</creator><creator>HUNTER RICHARD STEPHEN</creator><creator>FAI WONG CHUNG</creator><scope>EVB</scope></search><sort><creationdate>20100330</creationdate><title>DUAL REDUNDANT FAULT TOLERANT ELECTRONIC SYSTEM AND METHOD</title><author>CHYE GERALD LEE THIAN ; HUNTER RICHARD STEPHEN ; FAI WONG CHUNG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_SG159415A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><toplevel>online_resources</toplevel><creatorcontrib>CHYE GERALD LEE THIAN</creatorcontrib><creatorcontrib>HUNTER RICHARD STEPHEN</creatorcontrib><creatorcontrib>FAI WONG CHUNG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHYE GERALD LEE THIAN</au><au>HUNTER RICHARD STEPHEN</au><au>FAI WONG CHUNG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>DUAL REDUNDANT FAULT TOLERANT ELECTRONIC SYSTEM AND METHOD</title><date>2010-03-30</date><risdate>2010</risdate><abstract>Embodiments of the present invention provide a fault tolerant system for electronic components, the system comprising: a first Versa Module Eurocard (VME) module located within a housing; and a second Versa Module Eurocard (VME) module located within the housing; wherein the first and second VME modules are functionality. Each of the first and second modules may be located on a single backplane. Each of the first and second modules may further include: a plurality of card slots; a CPU card in one of the plurality of card slots; an input/output (I/O) card in one of the card slots and at least one input/output (I/O) channel providing an external connection to the system, the I/O channel being electrically connected to a plurality of user defined I/O connections on each of the VME modules.</abstract><oa>free_for_read</oa></addata></record> |
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title | DUAL REDUNDANT FAULT TOLERANT ELECTRONIC SYSTEM AND METHOD |
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