MULTI-DIE IC PACKAGE AND MANUFACTURING METHOD

MULTI-DIE IC PACKAGE AND MANUFACTURING METHOD

A method for manufacturing integrated circuit packages (100, 200, 300) and a multi-chip integrated circuit package (100, 200, 300) are disclosed. A first die (110) is attached onto a first side of a set of leads of a leadframe (130), an adhesive (350) is applied onto the set of leads at a second sid...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: WANG, CHUEN KHIANG, SUN, YI SHENG, ANTHONY, TAN, HIEN BOON, LAW, TEIK LYK, CLIFTON, LIU, HAO, BIDIN, RAHAMAT
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:A method for manufacturing integrated circuit packages (100, 200, 300) and a multi-chip integrated circuit package (100, 200, 300) are disclosed. A first die (110) is attached onto a first side of a set of leads of a leadframe (130), an adhesive (350) is applied onto the set of leads at a second side opposite to the first side. A second die (120) is attached onto the adhesive (350). The adhesive fills into the gaps between the leads. The adhesive is then cured. The adhesive attaching the second die fills the a s between the leads so that to avoid formation of internal cavities in the package.