Precision, high speed delay system for providing delayed clock edges with new delay values every clock period

A precision delay system (67, 70, 120) allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements (61, 62, 73, 101, 102) are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry (75, 121). The...

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Hauptverfasser:	BARNES, ROBERT, K, BAILEY, RANDY, L
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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creator	BARNES, ROBERT, K BAILEY, RANDY, L
description	A precision delay system (67, 70, 120) allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements (61, 62, 73, 101, 102) are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry (75, 121). The system (67, 70, 120) allows the use of delay elements (61, 62, 73, 101 , 102) with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_SG127673A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>SG127673A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_SG127673A13</originalsourceid><addsrcrecordid>eNqFy80KwjAQBOBePIj6DO4D6KEW7FnEn6Og9xKSabOYJiFbW_r2Fuzd08DMN8usfSRoFg5-R5YbSxIBQwZOjSSjdGipDoliCj0b9s1vmoh2Qb8JpoHQwJ0lj2H-9cp9phY90ji7iMTBrLNFrZxgM-cq214vr_N9jxgqSFQaHl31vOWH8lgWp7z4L75LsUE5</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Precision, high speed delay system for providing delayed clock edges with new delay values every clock period</title><source>esp@cenet</source><creator>BARNES, ROBERT, K ; BAILEY, RANDY, L</creator><creatorcontrib>BARNES, ROBERT, K ; BAILEY, RANDY, L</creatorcontrib><description>A precision delay system (67, 70, 120) allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements (61, 62, 73, 101, 102) are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry (75, 121). The system (67, 70, 120) allows the use of delay elements (61, 62, 73, 101 , 102) with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.</description><language>eng</language><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES ; BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE</subject><creationdate>2006</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20061229&DB=EPODOC&CC=SG&NR=127673A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20061229&DB=EPODOC&CC=SG&NR=127673A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BARNES, ROBERT, K</creatorcontrib><creatorcontrib>BAILEY, RANDY, L</creatorcontrib><title>Precision, high speed delay system for providing delayed clock edges with new delay values every clock period</title><description>A precision delay system (67, 70, 120) allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements (61, 62, 73, 101, 102) are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry (75, 121). The system (67, 70, 120) allows the use of delay elements (61, 62, 73, 101 , 102) with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.</description><subject>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</subject><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2006</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqFy80KwjAQBOBePIj6DO4D6KEW7FnEn6Og9xKSabOYJiFbW_r2Fuzd08DMN8usfSRoFg5-R5YbSxIBQwZOjSSjdGipDoliCj0b9s1vmoh2Qb8JpoHQwJ0lj2H-9cp9phY90ji7iMTBrLNFrZxgM-cq214vr_N9jxgqSFQaHl31vOWH8lgWp7z4L75LsUE5</recordid><startdate>20061229</startdate><enddate>20061229</enddate><creator>BARNES, ROBERT, K</creator><creator>BAILEY, RANDY, L</creator><scope>EVB</scope></search><sort><creationdate>20061229</creationdate><title>Precision, high speed delay system for providing delayed clock edges with new delay values every clock period</title><author>BARNES, ROBERT, K ; BAILEY, RANDY, L</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_SG127673A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2006</creationdate><topic>AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES</topic><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>BARNES, ROBERT, K</creatorcontrib><creatorcontrib>BAILEY, RANDY, L</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BARNES, ROBERT, K</au><au>BAILEY, RANDY, L</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Precision, high speed delay system for providing delayed clock edges with new delay values every clock period</title><date>2006-12-29</date><risdate>2006</risdate><abstract>A precision delay system (67, 70, 120) allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements (61, 62, 73, 101, 102) are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry (75, 121). The system (67, 70, 120) allows the use of delay elements (61, 62, 73, 101 , 102) with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.</abstract><oa>free_for_read</oa></addata></record>
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subjects	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
title	Precision, high speed delay system for providing delayed clock edges with new delay values every clock period
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