Precision, high speed delay system for providing delayed clock edges with new delay values every clock period

A precision delay system (67, 70, 120) allowing clock edges to be delayed with new delay values every clock period T. The internal delay elements (61, 62, 73, 101, 102) are reprogrammed every clock cycle with reprogramming transients suppressed by clock independent blanking circuitry (75, 121). The system (67, 70, 120) allows the use of delay elements (61, 62, 73, 101 , 102) with a maximum delay of one-half (T/2) the clock period to continuously span a full clock cycle T delay range with full cycle-by-cycle reprogramming.