METOD FOR FRAMSTELLNING AV INTEGRERADE KRETSAR

Integrated circuits of high density are fabricated in a simplified process which allows both the use of multiple conducting layers in a dielectric above a semiconductor substrate, such as a polycrystalline silicon (polysilicon) field shield and metal interconnection lines, while also making provision for very precise alignment of subsequent layers to diffusions. A doped oxide containing a suitable dopant, such as arsenic in the case of a p-type silicon substrate, is deposited on the substrate. A pattern corresponding to desired diffusions is generated by normal photolithographic and etching techniques. A second, undoped oxide layer is thermally grown over the semiconductor substrate with dopant from the doped oxide simultaneously diffusing into areas of the substrate underlying the doped oxide. The undoped oxide serves to prevent autodoping. Thermally growing the undoped oxide layer converts a layer of the semiconductor surface not covered by doped oxide to the undoped oxide. Both oxide layers are then removed, leaving slight steps at the surface of the semiconductor substrate around the diffusion. The slight steps serve to allow very precise alignment of masks for subsequent process steps. Otherwise, the structure produced is very planar. An insulating layer, desirably a composite of silicon dioxide and silicon nitride in the case of a silicon substrate, is then formed on the substrate, followed by a layer of polycrystalline semiconductor, desirably doped to provide high conductivity. Openings are then etched in the polycrystalline semiconductor layer to allow formation of gate electrodes of FET's, contact to the substrate, and contact of a subsequent interconnection metallization to diffusions in some of the circuits. A second insulating layer, such as silicon dioxide, is then grown on the polycrystalline semiconductor layer. Contact holes are then made to diffusions in the substrate, the substrate itself, and the polycrystalline silicon. The deposition and etching of an interconnection layer on the second insulating layer completes fabrication of the integrated circuit.