SE375666

1,168,154. Digital transversal filter. PHILIPS ELECTRONIC & ASSOCIATED INDUSTRIES Ltd. 2 March, 1967 [5 March, 19661, No. 9908/67. Heading H4R. In a filter the analogue signals to be filtered are converted to digital form and applied to a shift register which has a shift period less than half the period of the highest frequency in the analogue input. The signals at the outputs of the various stages of the shift register are decoded to analogue form, and combined in the appropriate proportions and polarities to provide the required filtered output. A further low-pass filter removes the quantization noise. The signals may be combined before or after decoding, or the two operations performed simultaneously. The analogue signals may be coded by delta modulation or p.c.m. The system is equivalent to a transversal filter with the tapped delay line replaced by the shift register, to provide a digital delay, and consequent conversion of the analogue signal to and from digital form. Such a filter provides, by the suitable choice of combining proportions and polarities, any desired amplitude-frequency characteristic, e.g. of sinusoidal or cosinusoidal form, with a linear phase-frequency characteristic. Fig. 4 shows one embodiment in which an analogue signal from source 1 is converted to digital form in the delta modulator 2 and the resulting signals passed via a pulse lengthener 25 to the shift register 8 which is stepped on at the same rate as the sampling frequency of the delta modulator. The outputs of the shift register stages are applied, either direct or via an inverter amplifier, to a combining circuit including resistors 27 to 34 where the outputs are combined with appropriate weighting to give the required filter response. The combined signal is then decoded in a decoder 24, which for the delta modulated signal comprises an integrator circuit. The filter 26 is a low-pass filter to remove quantization noise. It is suggested that since the decoder is effectively a filter the decoder 6 which is an integral part of the delta modulator could be replaced by a suitable combining circuit on the shift register outputs. In addition, the series arrangement of shift register stages may be replaced by a parallel arrangement, Fig. 8 (not shown). In the embodiment of Fig. 9 the analogue signal is coded into six digit p.c.m. and the resulting signal, in parallel binary form, is fed into parallel shift register stages 69-75, the signals in each of which are decoded by a res