SE364155

1,263,832. Pulse code modulation system. WESTERN ELECTRIC CO. Inc. 24 Sept., 1970 [26 Sept., 1969], No. 45468/70. Heading G4H. In an analogue to digital system in which the change in analogue signal is encoded in a threebit code, extra levels are obtained by dispensing with the sign bit for the highest and lowest levels, the levels being symmetrical about zero. The input signal is fed to a subtractor 102 where the previously coded sample is subtracted from the input. The difference signal is then fed via sampler 103 to threshold network 104. The output of network 104 is then fed to logic circuit 105 which combines the highest and lowest levels. Thus if a signal has a level corresponding to + 4 or - 4 it produces a pulse on line H. A Œ4 output is produced provided the previous output is of the same polarity, if it is of opposite polarity an output at the appropriate 3 level is produced. The positive outputs of logic circuit 105 are fed to logic circuit 108 which separates the highest and lowest levels and, these together with the remaining outputs are fed to digital to analogue converter 107. The output of 107 is fed via integrator 110 back to subtractor 102. The output of logic circuit 105 is also fed to code converter 106 and then transmitted. The logic circuit 105, Fig. 2, has a delay unit 203 which feeds the preceding output from the + 1 threshold, always present for positive signals, to AND gate 201 and inhibit terminal of AND gate 202. Thus if the preceding pulse is positive, gate 201 is enabled and gate 202 is inhibited. If the signal is negative, gate 202 is enabled and gate 201 is inhibited. Thus in the event of a +4 pulse being preceded by a negative pulse an output is obtained on the +3 line and vice versa. The logic circuit 108, Fig. 3, for separating the highest and lowest levels has a delay 302 through which the + 1 to +3 levels are fed to AND gate 303 and an inhibit terminal of AND 304. Thus if the previous pulse was positive AND gate 303 is enabled to produce an output representing +4 if a Œ4 pulse is present. Similarly a preceding negative pulse causes gate 304 to be enabled so that the Œ4 pulse appears at - 4. Code groups received by the receiver, Fig. 1 first pass through a code converter which produces an output on one of eight lines. These then pass to digital to analogue converter 123 via a logic circuit 122 of similar construction to logic circuit 108 used in the encoder. The output of the digital to analogue converter is then integra