TRANSISTOR WITH METAL-OXIDE-SEMICONDUCTOR STRUCTURE ON SILICON-ON-INSULATOR SUBSTRATE

FIELD: electrical engineering.SUBSTANCE: invention relates to the technology for fabrication of integral circuits based on complementary transistors with a metal-oxide-semiconductor structure using silicon-on-insulator (SOI) substrates. In the transistor with a metal-oxide-semiconductor structure on a silicon-on-insulator substrate, including fine-slit insulation regions, the region of the well of the retrograde profile of Type 2 admixture distribution with depth equal to the whole of the thickness of the silicon layer on the insulator, the region of a polysilicon gate alloyed with Type 2 admixture ions, regions lightly alloyed with Type 1 admixture (LDD), a spacer, a drain region formed on one side of the gate with highly alloyed Type 1 admixture ions with depth equal to the whole of the thickness of the silicon layer on the insulator, a source region formed on the other side of the gate, and the region of contact with the well formed by Type 2 admixture, electrically connected to the source via a silicide, the region of highly alloyed contact with the well is positioned under the source region and has width equal to that of the source, the electrical connection of the source regions to the well via a silicide occurring in the groove formed within the source region, the groove depth equal to or in excess of that of the source region and the groove width equal to that of the source.EFFECT: reduction of total planar area of source-contact regions, decrease of electrical resistivity of the contact with the well due to reduction of the pathway of minor carriers flow from the well region to the silicide region and reduction of reduction of the silicide contact resistivity to the highly alloyed region of contacts with the well, increase of radiation tolerance due to the highly alloyed region of contacts with the well preventing appearance of a bottom parasitic transistor conductive channel in the corresponding part of the well.13 dwg, 2 tbl Изобретение относится к технологии изготовления интегральных схем на комплементарных транзисторах со структурой метал-окисел-полупроводник (КМОП ИС), с использованием подложек кремний на изоляторе (КНИ). Технический результат изобретения заключается в уменьшении суммарной планарной площади областей исток-контакт; в уменьшении электросопротивления контакта к карману, за счет сокращения пути протекания неосновных носителей из области кармана к области силицида, а также снижения контактного сопротивления силицида к высоколегиро