VIRTUALLY TAGGED INSTRUCTION CACHE WITH PHYSICALLY TAGGED BEHAVIOUR

FIELD: information technology. ^ SUBSTANCE: system contains a virtually tagged instruction cache; a means for address translation which responds to an address translation invalidate instruction; and a control logic circuit configured to invalidate not all entries in the virtually tagged instruction...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SARTORIUS TOMAS EHNDRJU, STRITT DAREN JUDZHIN, SMIT RODNI UEHJN
Format:	Patent
Sprache:	eng ; rus
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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