MARKER SEPARATING DEVICE FOR FRAME SYNCHRONIZATION SYSTEM

FIELD: electrical communications; frame synchronization of receivers in digital data transfer systems. ^ SUBSTANCE: proposed marker separating device for frame synchronization system has series-connected K analysis stages of which second through (K - 1) stages are identical and made in the form of three-bit comparison-result shaping units; outputs of two preceding analysis stages are connected to inputs of one respective component of preceding analysis stage and outputs of three-bit comparison result shaping unit of (K - 1) analysis stage are connected to K analysis stage made in the form of final analyzed component unit; first analysis stage has shift register in the form of series-connected D flip-flops; input of first D flip-flop and output of last one function as data input and data output of device; each D flip-flop of shift register has reference code word setting input and marker length adjustment input; each adjacent pair of shift-register D flip-flops is incorporated in each of N intermediate-analysis units of first analysis stage; novelty is that introduced in each of N intermediate analysis units of first analysis stage are five-bit comparison-result shaping units whose inputs are connected to respective three-bit outputs of each pair of intermediate analysis units and that introduced in each of series-connected second through (K - 1) analysis stages are two-bit comparison-result shaping units; connected to input of each three-bit comparison-result unit and to that of each two-bit comparison-result shaping unit of second analysis stage are outputs of respective pair of five-bit comparison-result shaping units of first analysis stage; connected to inputs of each three-bit comparison result shaping unit and of two-bit comparison-result shaping unit in each third through (K - 1) next analysis stages are outputs of respective pair of five-bit comparison-result shaping units; outputs of five-bit comparison-result shaping unit of analysis stage (K - 1) are connected to respective additional inputs of final analyzing component of analysis stage K whose second inputs function as additional error number setting inputs in frame synchronization signal and output, as frame synchronization one. ^ EFFECT: enhanced noise immunity and speed. ^ 1 cl, 4 dwg