METHOD FOR PRODUCING VERTICAL P-N-P TRANSISTOR AS PART OF INTEGRATED CIRCUIT

FIELD: integrated circuits using bipolar vertical p-n-p transistors. SUBSTANCE: method involves rendering near-surface layer amorphous and introducing p-type dope at point of future location of buried p+-type layers in single implanting process using dope BF2, recrystallizing and baking of amorphous...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	SAMSONOV E.S, SHVARTS K.-G.M, DZJUBANOVA V.V, LUKASEVICH M.I, SHEVCHENKO A.P, GORNEV E.S, LOKTEV A.N
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	FIELD: integrated circuits using bipolar vertical p-n-p transistors. SUBSTANCE: method involves rendering near-surface layer amorphous and introducing p-type dope at point of future location of buried p+-type layers in single implanting process using dope BF2, recrystallizing and baking of amorphous layer, settling down epitaxial layer forming side insulation, producing surface dielectric, forming collector and base regions of transistor, forming base region of transistor, forming emitter. EFFECT: facilitated procedure. 2 cl, 7 dwgo