REDUCED PIN COUNT INTERFACE

REDUCED PIN COUNT INTERFACE

An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive as...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: DEVINE, QUINN, FROELICH, DAN, SHARMA, DEBENDRA DAS, LIM, SU WEI, TENNANT, BRUCE, JEN, MICHELLE
Format: Patent
Sprache:eng ; pol
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:An apparatus is provided that includes a set of registers, and an interface of a computing block. The computing block includes one of a physical layer block or a media access control layer block. The interface includes one or more pins to transmit asynchronous signals, one or more pins to receive asynchronous signals, and a set of pins to communicate particular signals to access the set of registers, where a set of control and status signals of a defined interface are mapped to respective bits of the set of registers.