Konfigureringsstyring i en programmerbar logisk innretning

A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists...

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Bibliographische Detailangaben
Hauptverfasser: BERGER NEAL, TAM EUGENE JINGLUN, SAIKI WILLIAM J, GONGWER GEOFFREY S, FAHEY JR JAMES, RAMAMURTHY SRINIVAS
Format: Patent
Sprache:nor
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Zusammenfassung:A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists of a Configuration Latch, and each configuration latch has an output used as a configuration control signal within an output logic macrocell. The configuration register's input signal is selectably provided from either a set of serially connected configuration bit non-volatile element sense latches or from the JTAG Test Data In (TDI) data pin for reconfiguration, prototyping, and testing.